rev. 4750a?audr?11/03 features reference oscillator up to 15 mhz two programmable 16-bit dividers adjustable from 2 to 65535 fine tuning steps ?am 1khz ?fm 2khz four programmable switching outputs (open drain up to 15 v) integrated loop-push-pull stage for am/fm high signal/noise ratio description the U4285BM is an integrated circuit in bicmos technology for frequency synthesiz- ers. it performs all the functions of a pll radio tuning system and is controlled by a 2-wire bus. the device is designed for all frequency synthesizer applications in radio receivers, as well as for rds (radio data system) applications. figure 1. block diagram r-divider n-divider bus interface oscillator phase current sources switching outputs am/fm 18 19 2 3 4 9 11 oscout oscin scl as fmosc amosc sda 5 678 10 1 20 swo1 swo4 swo2 swo3 14 15 16 17 12 13 pdam pdamo va c pdfmo pdfm gnd2 gnd1 dd v switch detector am/fm pll with 4 switches U4285BM
2 U4285BM 4750a?audr?11/03 pin configuration figure 2. pinning sso20 1 2 3 4 5 6 7 8 13 14 15 16 17 18 19 20 U4285BM scl sda as swo1 swo2 swo3 swo4 gnd1 oscout oscin c va pdamo pdam pdfm v dd 9 11 12 fmosc gnd2 pdfmo amosc 10 pin description pin symbol function 1v dd supply voltage 2sclbus clock 3sdabus data 4 as address selection 5 swo1 switching output 1 6 swo2 switching output 2 7 swo3 switching output 3 8 swo4 switching output 4 9 fmosc fm oscillator input 10 gnd2 ground 2 (analog) 11 amosc am oscillator input 12 pdfmo fm analog output 13 pdfm fm current output 14 pdam am current output 15 pdamo am analog output 16 va analog supply voltage 17 c capacitor 18 oscin oscillator input 19 oscout oscillator output 20 gnd1 ground 1 (digital)
3 U4285BM 4750a?audr?11/03 functional description the U4285BM is controlled via the 2-wire bus. one module address byte, two subad- dress bytes and five data bytes enable programming. the module address contains a programmable address bit a 1, which (along with address select input as, pin 4), enables the operation of two U4285BM devices in one system. if bit a 1 is identical with the status of the address select input as, the chip is selected. the subaddress determines which of the data bytes is transmitted first. if the subad- dress of the r-divider is transmitted, the sequence of the next data bytes is db 0 (status), db 1 and db 2. if the subaddress of the n-divider is transmitted, the sequence of the next data bytes is db 3 and db 4. the bit organization of the module address, subaddress and 5 data bytes is shown in table ?bit organization? on page 7. each transmission on the bus begins with the "start" condition and has to be ended by the "stop" condition (see table ?transmission protocol? on page 7). the integrated circuit U4285BM has two separate inputs for the am and fm oscillators. pre-amplified am and fm signals are fed to the 16 bit n-divider via the am/fm switch. the am/fm switch is software controlled. tuning steps can be selected by the 16 bit r-divider. furthermore, the device provides a digital memory phase detector and two separate current sources for am and fm amplifiers (charge pump) as given in the table ?electri- cal characteristics? on page 4. the separate current sources (charge pumps) allow independent gain adjustment, providing high current for high-speed tuning and low cur- rent for stable tuning. note: 1. corresponding to the application circuit (figure 8 on page 8) absolute maximum ratings stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability . parameters pins symbol value unit supply voltage 1 v dd -0.3 to +6 v input voltage 2, 3, 4, 9, 11, 18, 19 v i -0.3 to v dd + 0.3 v output current 3, 5, 6, 7, 8 i o -1 to +5 ma output drain voltage 5, 6, 7, 8 v od 15 v analog supply voltage with 220 ? serial resistance 2 minutes (1) 16 v a v a 6 to 15 24 v v output current 12, 15 i ao -1 to +20 ma ambient temperature range t amb -30 to +85 c storage temperature range t stg -40 to +125 c junction temperature t j 125 c electrostatic handling (modified mil std 883 d method 3015.7: all supply pins connected together) v esd 1000 v
4 U4285BM 4750a?audr?11/03 thermal resistance parameters symbol value unit junction ambient r thja 160 k/w electrical characteristics v dd = 5 v, v a = 10 v, t amb = 25 c, unless otherwise specified parameters test conditions pins symbol min. typ. max. unit supply voltage 1 v dd 4.5 5.0 5.5 v quiescent supply current am mode/fm mode 1 i dd 4.0 7.0 ma fm input sensitivity, r g = 50 ? , fmosc f i = 70 to 120 mhz 9 v sfm 40 mv rms f i = 160 mhz 9 v sfm 150 mv rms am input sensitivity, r g = 50 ? , amosc f i = 0.6 to 35 mhz 11 v sam 40 mv rms oscillator input sensitivity, r g = 50 ? , oscin f i = 0.1 to 15 mhz 18 v sosc 100 mv rms switching output swo1, swo2, swo3, swo4 (open drain) output voltage low i l = 1 ma 5, 6, 7, 8 v swol 100 400 ma output leakage current high v5, v6, v7, v8 = 10 v 5, 6, 7, 8 i ohl 100 na phase detector pdfm output current 1 13 i pdfm 1600 2000 2400 a output current 2 13 i pdfm 400 500 600 a leakage current 13 i pdfml 20 na phase detector pdam output current 1 14 i pdam 160 200 240 a output current 2 14 i pdam 40 50 60 a leakage current 14 i pdaml 20 a analog output pdfmo, pdamo saturation voltage low i = 15 ma 12, 15 v satl 200 400 mw saturation voltage high i = 15 ma 12, 15 v sath 9.5 9.95 v bus scl, sda, as input voltage high 2, 3, 4 v ibus 3.0 v dd v input voltage low 2, 3, 4 v ibus 01.5v output voltage acknowledge low i sda = 3 ma 3 v o 0.4 v clock frequency 2 f scl 100 khz rise time sda, scl 2, 3 t r 1s fall time sda, scl 2, 3 t f 300 ns period of scl high high 2 t h 4.0 s period of scl low low 2 t l 4.7 s
5 U4285BM 4750a?audr?11/03 note: 1. this is a period of time where the bus must be free from data transmission before a new transmission can be started. figure 3. fm input sensitivity, t = 85 c figure 4. fm input sensitivity, t = -30 c set-up time start condition t ssta 4.7 s data t sdat 250 s stop condition t sstop 4.7 s time space (1) t wsta 4.7 s hold time start condition t hsta 4.0 s data t hdat 0s electrical characteristics (continued) v dd = 5 v, v a = 10 v, t amb = 25 c, unless otherwise specified parameters test conditions pins symbol min. typ. max. unit 0.0 2.0 4.0 6.0 8.0 10.0 12.0 14.0 20.0 60.0 100.0 f ifm (mhz) v sfm (ma) t = 85c v dd = 5.5 v 5.0 v 4.5 v 0.0 2.0 4.0 6.0 8.0 10.0 12.0 14.0 20.0 60.0 100.0 f ifm (mhz) v sfm (ma) t = -30c v dd = 5.5 v 5.0 v 4.5 v
6 U4285BM 4750a?audr?11/03 figure 5. am input sensitivity, t = 85 c figure 6. am input sensitivity, t = -30 c figure 7. bus timing 1.0 10.0 100.0 0 1 10 100 v dd (v) f sysclk (khz) t = 85c v dd = 5.5 v 5.0 v 4.5 v 1.0 10.0 100.0 0110100 v dd (v) f sysclk (khz) t = -30c v dd = 5.5 v 5.0 v 4.5 v t wsta ps t hsta t l t r sda scl t hdat p t hsta t f t h t ssta t sstop p = stop, s = start t hdat
7 U4285BM 4750a?audr?11/03 bit organization table 1. function mode transmission protocol note: s = start, p = stop, a = acknowledge msb lsb module address 1 1 0 0 1 0 0/1 0 a7 a6 a5 a4 a3 a2 a1 a0 subaddress (r-divider) x x x 0 0 1 x x subaddress (n-divider) x x x x 1 1 x x data byte 0 (status) swo1 swo2 swo3 swo4 am/fm pd - ana pd - pol pd - cur d7 d6 d5 d4 d3 d2 d1 d0 data byte 1 2 15 r-divider 2 8 data byte 2 2 7 r-divider 2 0 data byte 3 2 15 n-divider 2 8 data byte 4 2 7 n-divider 2 0 bit description mode low high d3 am/fm fm operation am operation d2 pd - ana pd analog test d1 pd - pol negative polarity positive polarity d0 pd - cur output current 2 output current 1 msb lsb s address a subaddress a data 0 a data 1 a data 2 a p a0 a7 r-divider msb lsb s address a subaddress a data 3 a data 4 a p a0 a7 n-divider
8 U4285BM 4750a?audr?11/03 figure 8. application circuit recommendations for applications c 3 = 100 nf should be very close to pin 1 (v dd ) and pin 20 (gnd 1) gnd 2 (pin 10 - analog ground) and gnd 1 (pin - digital ground) must be connected according to figure 8 4 mhz crystal must be very close to pin 18 and pin 19 components of the charge pump (c 1 /r 1 for am and c 2 /r 2 for fm) should be very close to pin 14 with respect to pin 13 figure 9. pcb layout 16 123 4 u4289bm 56 7 8 15 14 13 12 11 10 9 4 mhz 27 pf 27 pf amosc fmosc 12k ? 12k ? 5v 100 nf 6 to 15 v 110 ? 110 ? 100 f 16 v c 1 *) c 5 *) r 1 *) r 2 *) c 2 *) 3 k ? c 6 *) c 3 100 f 6.3 v 27 ? c 4 2.2 nf 100 nf 1 nf *) values depend on the step frequency and used varicaps 16 123 4 56 7 8 15 14 13 12 11 10 9 c 1 c 3 c 4 v dd gnd c 2
9 U4285BM 4750a?audr?11/03 package information ordering information extended type number package remarks U4285BM-mfs sso20 plastic ? U4285BM-mfsg3 sso20 plastic taping according to iec-286-3 technical drawings according to din specifications package sso20 dimensions in mm 6.75 6.50 0.25 0.65 5.85 1.30 0.15 0.05 5.7 5.3 4.5 4.3 6.6 6.3 0.1 5 20 11 110
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